80 lines
1.9 KiB
Verilog
80 lines
1.9 KiB
Verilog
module top;
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reg pass;
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real a, b;
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integer i;
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wire real b1 = 42.0 + 10/100;
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wire real b2 = a + 10/100;
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wire real b3 = 42.0 + i/100;
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wire real b4 = a + i/100;
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initial begin
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pass = 1'b1;
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// Check the compiler for the whole expression.
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b = 42.0 + 10/100;
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if (b != 42.0) begin
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$display("FAILED: compiler constant, expected 42.0, got %6.1f", b);
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pass = 1'b0;
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end
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// Check the compiler for just the division.
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a = 42;
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b = a + 10/100;
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if (b != 42.0) begin
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$display("FAILED: compiler constant div., expected 42.0, got %6.1f", b);
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pass = 1'b0;
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end
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// Check the run time with a constant sum value (just the division).
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i = 10;
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b = 42.0 + i/100;
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if (b != 42.0) begin
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$display("FAILED: runtime constant real, expected 42.0, got %6.1f", b);
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pass = 1'b0;
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end
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// Check the original expression.
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b = a + i/100;
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if (b != 42.0) begin
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$display("FAILED: runtime, expected 42.0, got %6.1f", b);
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pass = 1'b0;
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end
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// Check the ternary operator with one clause needing to be converted.
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b = (i === 10) ? i/100 : 1.0;
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if (b != 0.0) begin
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$display("FAILED: runtime (ternary), expected 0.0, got %6.1f", b);
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pass = 1'b0;
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end
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b = |i;
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if (b != 1.0) begin
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$display("FAILED: runtime (reduction), expected 1.0, got %6.1f", b);
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pass = 1'b0;
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end
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// Check the continuous assigns.
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#1;
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if (b1 != 42.0) begin
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$display("FAILED: CA test 1, expected 42.0, got %6.1f", b1);
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pass = 1'b0;
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end
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if (b2 != 42.0) begin
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$display("FAILED: CA test 2, expected 42.0, got %6.1f", b2);
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pass = 1'b0;
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end
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if (b3 != 42.0) begin
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$display("FAILED: CA test 3, expected 42.0, got %6.1f", b3);
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pass = 1'b0;
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end
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if (b4 != 42.0) begin
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$display("FAILED: CA test 4, expected 42.0, got %6.1f", b4);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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