26 lines
496 B
Verilog
26 lines
496 B
Verilog
`timescale 1ns/1ps
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module test;
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reg in, pass;
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wire out;
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assign #(1?2:1) out = in;
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// assign #(1+1) out = in;
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initial begin
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pass = 1'b1;
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in = 1'b0;
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#1.999;
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if (out !== 1'bx) begin
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$display("Failed signal at begining, expected 1'bx, got %b", out);
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pass = 1'b0;
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end
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#0.002;
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if (out !== in) begin
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$display("Failed signal at end, expected %b, got %b", in, out);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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