77 lines
1.8 KiB
Verilog
77 lines
1.8 KiB
Verilog
module top;
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reg pass;
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reg [7:0] vec;
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integer off;
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time delay;
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event trig;
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initial begin
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pass = 1'b1;
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delay = 1;
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// Assign before the vector (constant delay).
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vec = 8'hff;
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off = -1;
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vec[off] <= #1 1'b0;
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#2 if (vec !== 8'hff) begin
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$display("Failed the before vector (C) test, expected 8'hff, got %h",
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vec);
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pass = 1'b0;
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end
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// Assign after the vector (constant delay).
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vec = 8'hff;
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off = 8;
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vec[off] <= #1 1'b0;
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#2 if (vec !== 8'hff) begin
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$display("Failed the after vector (C) test, expected 8'hff, got %h",
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vec);
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pass = 1'b0;
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end
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// Assign before the vector (variable delay).
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vec = 8'hff;
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off = -1;
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vec[off] <= #(delay) 1'b0;
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#2 if (vec !== 8'hff) begin
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$display("Failed the before vector (V) test, expected 8'hff, got %h",
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vec);
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pass = 1'b0;
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end
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// Assign after the vector (variable delay).
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vec = 8'hff;
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off = 8;
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vec[off] <= #(delay) 1'b0;
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#2 if (vec !== 8'hff) begin
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$display("Failed the after vector (V) test, expected 8'hff, got %h",
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vec);
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pass = 1'b0;
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end
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// Assign before the vector (event trigger).
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vec = 8'hff;
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off = -1;
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vec[off] <= @(trig) 1'b0;
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->trig;
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#1 if (vec !== 8'hff) begin
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$display("Failed the before vector (E) test, expected 8'hff, got %h",
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vec);
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pass = 1'b0;
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end
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// Assign after the vector (event trigger).
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vec = 8'hff;
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off = 8;
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vec[off] <= @(trig) 1'b0;
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->trig;
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#1 if (vec !== 8'hff) begin
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$display("Failed the after vector (V) test, expected 8'hff, got %h",
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vec);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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