65 lines
1.5 KiB
Verilog
65 lines
1.5 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@telocity.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Test non-constant bit selects - causes compile error right now
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module test;
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reg clk;
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reg [1:0] in0;
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reg [1:0] in1;
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reg sel0,sel1;
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wire [1:0] q;
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dff2 u1 (q,clk,in0[sel0],in1[sel1]);
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initial
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begin
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clk = 0;
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in0 = 2'b0;
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in1 = 2'b0;
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sel0 = 1'b0;
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sel1 = 1'b1;
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#8;
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$display("initial val =%x",q);
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#8;
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if(q == 2'b0)
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$display("PASSED");
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else
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$display("FAILED");
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$finish ;
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end
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always #5 clk = ~clk;
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endmodule
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// This is just a dual dff
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module dff2 (q,clk,d0,d1);
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input clk,d0,d1;
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output [1:0] q;
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reg [1:0] q;
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always @(posedge clk)
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q <= {d1,d0};
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endmodule
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