67 lines
1.4 KiB
Verilog
67 lines
1.4 KiB
Verilog
module top;
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reg pass;
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wire [1:0] out;
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reg [1:0] drive_val;
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reg [1:0] oe_n;
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reg [2:0] pull_vec;
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reg [1:0] base;
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bufif0 bufs[1:0] (out, drive_val, oe_n);
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assign (pull0, pull1) out = pull_vec[base+:2];
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initial begin
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pass = 1'b1;
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base = 2'b00;
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pull_vec = 3'b000;
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oe_n = 2'b00;
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// Drive is selected.
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drive_val = 2'b00;
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#1;
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if (out !== drive_val) begin
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$display("Failed to drive 2'b00, got %b", out);
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pass = 1'b0;
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end
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drive_val = 1'b1;
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#1;
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if (out !== drive_val) begin
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$display("Failed to drive 2'b11, got %b", out);
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pass = 1'b0;
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end
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// The pull is selected (low).
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oe_n = 2'b11;
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drive_val = 2'b00;
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#1;
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if (out !== pull_vec[1:0]) begin
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$display("Failed pull #1, expected 2'b00, got %b", out);
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pass = 1'b0;
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end
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drive_val = 1'b1;
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#1;
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if (out !== pull_vec[1:0]) begin
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$display("Failed pull #2, expected 2'b00, got %b", out);
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pass = 1'b0;
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end
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// The pull is selected (high).
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pull_vec = 3'b111;
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drive_val = 2'b00;
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#1;
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if (out !== pull_vec[1:0]) begin
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$display("Failed pull #3, expected 2'b11, got %b", out);
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pass = 1'b0;
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end
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drive_val = 2'b11;
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if (out !== pull_vec[1:0]) begin
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$display("Failed pull #4, expected 2'b11, got %b", out);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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