22 lines
391 B
Verilog
22 lines
391 B
Verilog
module top;
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reg [7:0] a;
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reg [2:0] b;
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wire [7:0] y, z;
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assign y = a >> b;
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assign z = $signed(a) >> $signed(b);
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initial begin
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// Example vector
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a = 8'b10101010;
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b = 3'b101;
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#1;
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// Test for correctness
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if (y === z && y === 8'b00000101)
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$display("PASSED");
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else
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$display("FAILED, expected 8'b00000101, got %b/%b", y, z);
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end
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endmodule
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