26 lines
365 B
Verilog
26 lines
365 B
Verilog
module pr2533175();
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task fill_array;
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begin:block
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reg [7:0] array[3:0];
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integer i;
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for (i = 0; i < 4; i = i + 1) begin
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array[i] = i;
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end
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for (i = 0; i < 4; i = i + 1) begin
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if (array[i] != i) begin
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$display("FAILED: %0d != %0d", array[i], i);
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$finish;
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end
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end
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$display("PASSED");
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end
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endtask
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initial fill_array;
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endmodule
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