40 lines
784 B
Verilog
40 lines
784 B
Verilog
module main;
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reg a, b, reset, pass;
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always @*
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a = b | reset;
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always @* begin
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b = 1'b0;
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#2;
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b = a;
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end
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initial begin
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pass = 1'b1;
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reset = 1'b1;
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#1 if(b !== 1'b0) begin
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$display("FAILED initial zero for 1'b1, got %b", b);
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pass = 1'b0;
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end
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#2 if(b !== 1'b1) begin
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$display("FAILED initial set to 1'b1, got %b", b);
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pass = 1'b0;
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end
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// Since b is already 1'b1 reset can not change a to zero.
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reset = 1'b0;
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#1 if(b !== 1'b1) begin
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$display("FAILED block of initial zero for 1'b0, got %b", b);
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pass = 1'b0;
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end
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#2 if(b !== 1'b1) begin
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$display("FAILED block of initial set to 1'b0, got %b", b);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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