47 lines
992 B
Verilog
47 lines
992 B
Verilog
module top;
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reg pass;
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reg [1:0] in, shift, result;
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reg signed [1:0] ins;
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wire [1:0] ls = in << shift;
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wire [1:0] als = in <<< shift;
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wire [1:0] rs = in >> shift;
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wire [1:0] rs2 = in >>> shift;
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wire [1:0] ars = ins >> shift;
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initial begin
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pass = 1'b1;
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in = 2'b01;
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ins = 2'b10;
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shift = 2'bx1;
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#1
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if (ls !== 2'bxx) begin
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$display("Failed << (CA), expected 2'bxx, got %b", ls);
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pass = 1'b0;
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end
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if (als !== 2'bxx) begin
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$display("Failed <<< (CA), expected 2'bxx, got %b", als);
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pass = 1'b0;
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end
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if (rs !== 2'bxx) begin
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$display("Failed >> (CA), expected 2'bxx, got %b", rs);
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pass = 1'b0;
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end
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if (rs2 !== 2'bxx) begin
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$display("Failed >>> (CA), expected 2'bxx, got %b", rs2);
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pass = 1'b0;
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end
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if (ars !== 2'bxx) begin
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$display("Failed >>> (signed, CA), expected 2'bxx, got %b", ars);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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