63 lines
1.3 KiB
Verilog
63 lines
1.3 KiB
Verilog
module test ();
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parameter param = 3;
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reg [2:0] dummy;
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initial dummy = block.f(0);
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generate
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case (param)
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1, 2: if (param==1) begin : block
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function [2:0] f;
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input i;
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begin
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$display ("if param==1");
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f = param;
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end
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endfunction
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end else begin : block
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function [2:0] f;
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input i;
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begin
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$display ("else if param==2");
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f = param;
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end
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endfunction
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end
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4: begin : block
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function [2:0] f;
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input i;
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begin
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$display ("if param==4");
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f = param;
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end
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endfunction // f
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end
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endcase
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endgenerate
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endmodule
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module top ();
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test #(1) a();
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test #(2) b();
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test #(4) c();
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initial begin
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#1 if (a.dummy !== 1) begin
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$display("FAILED -- a.dummy = %d", a.dummy);
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$finish;
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end
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if (b.dummy !== 2) begin
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$display("FAILED -- b.dummy = %d", b.dummy);
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$finish;
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end
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if (c.dummy !== 4) begin
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$display("FAILED -- c.dummy = %d", c.dummy);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule
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