43 lines
852 B
Verilog
43 lines
852 B
Verilog
module top;
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reg passed;
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reg[1:0] in;
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integer where;
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always @(in) begin
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casez(in)
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2'b10: where = 1;
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2'bx?: where = 2; // MSB is X
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2'b??: where = 3; // The same as default.
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endcase
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end
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initial begin
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passed = 1'b1;
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in = 2'b10;
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#1 if (where != 1) begin
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$display("FAILED 2'b10 case, found case %d", where);
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passed = 1'b0;
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end
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in = 2'bx0;
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#1 if (where != 2) begin
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$display("FAILED 2'bx? case (1), found case %d", where);
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passed = 1'b0;
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end
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in = 2'bx1;
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#1 if (where != 2) begin
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$display("FAILED 2'bx? case (2), found case %d", where);
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passed = 1'b0;
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end
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in = 2'b00;
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#1 if (where != 3) begin
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$display("FAILED 2'b?? case, found case %d", where);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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