39 lines
944 B
Verilog
39 lines
944 B
Verilog
// Adapted from test case submitted by Geoff Blackman
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module pr2276163();
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function automatic integer f1;
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input integer in;
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f1 = in + 1;
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endfunction
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function integer f2;
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input integer in;
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f2 = in * 2;
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endfunction
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integer ret;
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initial begin
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ret = f1 ( f1 (1) );
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if (ret !== 3) begin
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$display("FAILED: expected 3, got %0d", ret);
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$finish;
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end
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ret = f1 ( f2 (2) );
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if (ret !== 5) begin
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$display("FAILED: expected 5, got %0d", ret);
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$finish;
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end
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ret = f2 ( f1 (3) );
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if (ret !== 8) begin
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$display("FAILED: expected 8, got %0d", ret);
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$finish;
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end
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ret = f2 ( f2 (4) );
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if (ret !== 16) begin
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$display("FAILED: expected 16, got %0d", ret);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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