108 lines
2.8 KiB
Verilog
108 lines
2.8 KiB
Verilog
module top;
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reg passed;
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reg signed[95:0] m_one, m_two, zero, one, two;
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// Both argument positive.
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reg signed[95:0] rem;
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wire signed[95:0] wrem = one % two;
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// First argument negative.
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reg signed[95:0] rem1n;
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wire signed[95:0] wrem1n = m_one % two;
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// Second argument negative.
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reg signed[95:0] rem2n;
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wire signed[95:0] wrem2n = one % m_two;
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// Both arguments negative.
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reg signed[95:0] rembn;
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wire signed[95:0] wrembn = m_one % m_two;
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// Divide by zero.
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reg signed[95:0] remd0;
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wire signed[95:0] wremd0 = one % zero;
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initial begin
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passed = 1'b1;
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m_one = 96'hffffffffffffffffffffffff;
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m_two = 96'hfffffffffffffffffffffffe;
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zero = 96'h000000000000000000000000;
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one = 96'h000000000000000000000001;
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two = 96'h000000000000000000000002;
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#1;
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// Both positive.
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if (wrem !== 96'h000000000000000000000001) begin
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$display("Failed: CA remainder, expected 96'h00...01, got %h",
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wrem);
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passed = 1'b0;
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end
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rem = one % two;
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if (rem !== 96'h000000000000000000000001) begin
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$display("Failed: remainder, expected 96'h00...01, got %h",
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rem);
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passed = 1'b0;
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end
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// First negative.
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if (wrem1n !== 96'hffffffffffffffffffffffff) begin
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$display("Failed: CA remainder (1n), expected 96'hff...ff, got %h",
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wrem1n);
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passed = 1'b0;
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end
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rem1n = m_one % two;
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if (rem1n !== 96'hffffffffffffffffffffffff) begin
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$display("Failed: remainder (1n), expected 96'hff...ff, got %h",
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rem1n);
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passed = 1'b0;
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end
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// Second negative.
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if (wrem2n !== 96'h000000000000000000000001) begin
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$display("Failed: CA remainder (2n), expected 96'h00...01, got %h",
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wrem2n);
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passed = 1'b0;
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end
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rem2n = one % m_two;
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if (rem2n !== 96'h000000000000000000000001) begin
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$display("Failed: remainder (2n), expected 96'h00...01, got %h",
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rem2n);
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passed = 1'b0;
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end
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// Both negative.
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if (wrembn !== 96'hffffffffffffffffffffffff) begin
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$display("Failed: CA remainder (bn), expected 96'hff...ff, got %h",
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wrembn);
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passed = 1'b0;
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end
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rembn = m_one % m_two;
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if (rembn !== 96'hffffffffffffffffffffffff) begin
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$display("Failed: remainder (bn), expected 96'hff...ff, got %h",
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rembn);
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passed = 1'b0;
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end
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// Divide by zero.
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if (wremd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
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$display("Failed: CA remainder (d0), expected 96'hxx...xx, got %h",
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wremd0);
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passed = 1'b0;
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end
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remd0 = one % zero;
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if (remd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin
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$display("Failed: remainder (d0), expected 96'hxx...xx, got %h",
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remd0);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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