18 lines
383 B
Verilog
18 lines
383 B
Verilog
module test();
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parameter N_N = 3;
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reg signed [2*N_N-1:0] val_neg;
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reg signed [2*N_N-1:0] val_pos;
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initial
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begin
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val_neg = {{N_N+1{1'b1}},{N_N-1{1'b0}}};
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val_pos = {{N_N+1{1'b0}},{N_N-1{1'b1}}};
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#1 $display("Var %d vs signed(concat) %d",
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val_neg,
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$signed({{N_N+1{1'b1}},{N_N-1{1'b0}}}));
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$finish(0);
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end // initial begin
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endmodule // test
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