28 lines
635 B
Verilog
28 lines
635 B
Verilog
module bug();
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wire [2:0] Value1 = 0;
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generate
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genvar i;
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for (i = 0; i < 8; i = i + 1) begin:Block
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wire [2:0] Value2;
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assign Value2 = Value1 + 7 - i;
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end
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endgenerate
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initial begin
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#1;
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$display("Block 0 value = %0d", Block[0].Value2);
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$display("Block 1 value = %0d", Block[1].Value2);
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$display("Block 2 value = %0d", Block[2].Value2);
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$display("Block 3 value = %0d", Block[3].Value2);
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$display("Block 4 value = %0d", Block[4].Value2);
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$display("Block 5 value = %0d", Block[5].Value2);
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$display("Block 6 value = %0d", Block[6].Value2);
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$display("Block 7 value = %0d", Block[7].Value2);
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end
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endmodule
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