32 lines
709 B
Verilog
32 lines
709 B
Verilog
`ifdef __ICARUS__
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`define SUPPORT_REAL_NETS_IN_IVTEST
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`endif
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module top;
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reg pass = 1'b1;
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integer scale = 2, offset = 1;
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real rin;
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`ifdef SUPPORT_REAL_NETS_IN_IVTEST
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wire real ress = scale * rin;
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wire real reso = rin + offset;
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`endif
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initial begin
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`ifdef SUPPORT_REAL_NETS_IN_IVTEST
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#1 if (ress != 0.0 || reso != 1.0) begin
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$display("FAILED: initial value, expected 0.0/1.0, got %f/%f", ress, reso);
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pass = 1'b0;
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end
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rin = 2.0;
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#1 if (ress != 4.0 || reso != 3.0) begin
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$display("FAILED: rin=%f, scale=%f, expected 2.0/2.0, got %f/%f", rin, scale, ress, reso);
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pass = 1'b0;
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end
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`endif
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if (pass)
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$display("PASSED");
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end
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endmodule
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