23 lines
377 B
Verilog
23 lines
377 B
Verilog
module top;
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reg pass = 1'b1;
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wire real rval;
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real in;
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assign rval = in + 2;
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initial begin
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// $monitor(rval,, in);
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in = 0;
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#1 in = 1;
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#1 in = 2;
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#1 if (pass) $display("PASSED");
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end
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always @(rval) begin
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if (rval != in + 2.0) begin
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$display("FAILED: expected %f, got %f", in + 2.0, rval);
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pass = 1'b0;
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end
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end
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endmodule
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