25 lines
379 B
Verilog
25 lines
379 B
Verilog
// Copyright 2008, Martin Whitaker.
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// This file may be freely copied for any purpose.
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module multiply();
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reg signed [31:0] A;
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reg signed [31:0] B;
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wire signed [63:0] Y;
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assign Y = A * B;
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initial begin
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A = -1;
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B = -1;
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#1 $display("(%0d)*(%0d) = %0d", A, B, Y);
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if (Y !== 64'd1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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