25 lines
622 B
Verilog
25 lines
622 B
Verilog
module top;
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reg [10*8-1:0] str [2:0];
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reg [31:0] idx [2:0];
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reg [4*8-1:0] pvstr, pvstr2;
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reg [15:0] pvidx, pvidx2, pvbase;
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initial begin
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pvstr = "S";
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pvstr2 = "SF";
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pvidx = 'd2;
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pvidx2 = 'd8;
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pvbase = 'd0;
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str[0] = "FAIL";
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str[1] = "PA";
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str[2] = "ED";
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idx[0] = 0;
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idx[1] = 1;
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idx[2] = 2;
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$write("%0s", str[idx[1]]); // This prints PA or FAIL.
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$write("%0s", pvstr[idx[0] +: 16]); // This adds an S.
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$write("%0s", pvstr2[pvidx2[pvbase +: 4] +: 8]); // This adds another S.
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$display("%0s", str[pvidx[pvbase +: 8]]); // This adds the ED.
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end
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endmodule
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