23 lines
482 B
Verilog
23 lines
482 B
Verilog
module top;
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reg pass = 1'b1;
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reg sel = 0;
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wire [2:0] out;
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pullup(out[0]);
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pullup(out[1]);
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assign out = sel ? 3'b000 : 3'bzzz;
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initial begin
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#1 if (out !== 3'bz11) begin
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$display("FAILED: initial value, expected 3'bz11, got %b", out);
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pass = 1'b0;
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end
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#1 sel = 1;
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#1 if (out !== 3'b000) begin
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$display("FAILED: final value, expected 3'b000, got %b", out);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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