22 lines
655 B
Verilog
22 lines
655 B
Verilog
/*
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* The base vpi_get() is not returning the correct result for
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* a signed value. There are obviously other problems as well.
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*/
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module top;
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reg [7:0] rval;
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reg signed [7:0] base; // This fails (no sign extension?).
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// reg signed [31:0] base; // This works on a 32 bit machine.
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// integer base; // And this works
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initial begin
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rval = 8'b10100101;
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for (base = 0; base > -8; base = base -1) begin
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$displayb("%3d %b ", base, rval[base +: 8], rval[base +: 8]);
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end
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$display;
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for (base = 0; base > -8; base = base -1) begin
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$displayb("%3d %b ", base+1, rval[base+1 +: 8], rval[base+1 +: 8]);
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end
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end
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endmodule
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