42 lines
1.0 KiB
Verilog
42 lines
1.0 KiB
Verilog
`ifdef __ICARUS__
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`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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`endif
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module top();
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reg pass = 1'b1;
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integer fp, i, n;
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reg [8:0] v;
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`ifndef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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reg [11:-4] w;
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`endif
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initial begin
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fp = $fopen("work/temp.txt", "w");
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for (i = 0; i < 4; i = i + 1) begin
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$fdisplay(fp, "%d", i + 16'he020);
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end
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$fclose(fp);
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fp = $fopen("work/temp.txt", "r");
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for (i = 0; i < 4; i = i + 1) begin
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v = 9'd0;
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// Use the following line and change the base in the a.out file
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// to -4 and the width to 16 to get correct functionality.
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//n = $fscanf(fp, " %d ", v[7:0]); // This uses the &PV<>
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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n = $fscanf(fp, " %d ", v[11:-4]); // This does not use &PV<> (bug)
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`else
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n = $fscanf(fp, " %d ", w);
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v = w[8:0];
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`endif
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if (v != 2) begin
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$display("FAILED: iteration %d, got %b, expected 9'b000000010", i, v);
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pass = 1'b0;
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end
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end
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$fclose(fp);
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if (pass) $display("PASSED");
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end
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endmodule
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