40 lines
712 B
Verilog
40 lines
712 B
Verilog
module main;
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generate
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genvar i;
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for( i=0; i<4; i=i+2 )
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begin : U
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reg [1:0] a;
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initial begin : V
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a = 2'b0;
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#10;
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a = i;
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end
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end
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endgenerate
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initial begin
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#5 ;
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if (U[0].V.a !== 2'd0) begin
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$display("FAILED -- U[0].V.a = %d", U[0].V.a);
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$finish;
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end
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if (U[2].V.a !== 2'd0) begin
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$display("FAILED -- U[2].V.a = %d", U[2].V.a);
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$finish;
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end
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#10 ;
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if (U[0].V.a !== 2'd0) begin
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$display("FAILED -- U[0].V.a = %d", U[0].V.a);
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$finish;
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end
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if (U[2].V.a !== 2'd2) begin
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$display("FAILED -- U[2].V.a = %d", U[2].V.a);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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