30 lines
466 B
Verilog
30 lines
466 B
Verilog
module main;
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reg clk;
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localparam integer TEST = 100;
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print #("PASSED", TEST) foo (clk);
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initial begin
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clk = 0;
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#1 clk = 1;
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#1 $finish;
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end
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endmodule // main
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module print (input wire clk);
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parameter message = "";
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parameter number = 0;
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always @(posedge clk) begin
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if (number !== 100) begin
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$display("FAILED -- number=%d\n", number);
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$finish;
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end
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$display("%s", message);
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end
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endmodule // print
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