40 lines
586 B
Verilog
40 lines
586 B
Verilog
// pr1958001
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module s_cmpGe( in00, in01, out00 );
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parameter bw_in00 = 32;
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parameter bw_in01 = 32;
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input signed [bw_in00-1:0] in00;
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input signed [bw_in01-1:0] in01;
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output out00;
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assign out00 = ( in00 >= in01 );
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endmodule
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module x;
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reg signed [31:0] a;
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reg signed b;
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wire c;
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s_cmpGe #(32, 1) inst(a, b, c);
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initial
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begin
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b = 0;
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a = -1;
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#1;
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$display("%d >= %d = %d", a, b, c);
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if (c !== 0) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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