37 lines
608 B
Verilog
37 lines
608 B
Verilog
module test;
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wire a;
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reg [20:0] b;
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assign a = ((b[20:4]) || (b[3] && b[2:0])) ? 1'b0 : 1'b1;
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initial begin
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b = 0;
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#1 if (a !== 1'b1) begin
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$display("FAILED -- b=%h, a=%b", b, a);
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$finish;
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end
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b = 8;
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#1 if (a !== 1'b1) begin
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$display("FAILED -- b=%h, a=%b", b, a);
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$finish;
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end
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b = 12;
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#1 if (a !== 1'b0) begin
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$display("FAILED -- b=%h, a=%b", b, a);
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$finish;
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end
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b = 16;
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#1 if (a !== 1'b0) begin
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$display("FAILED -- b=%h, a=%b", b, a);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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