52 lines
961 B
Verilog
52 lines
961 B
Verilog
`define DEV_TYPE "DEVICE 2"
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module top;
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parameter device = `DEV_TYPE;
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wire res;
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function is_dev1;
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input[8*20:1] device;
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reg is_device;
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begin
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if ((device == "DEVICE1") || (device == "DEVICE 1"))
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is_device = 1;
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else
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is_device = 0;
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is_dev1 = is_device;
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end
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endfunction
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function is_dev2;
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input[8*20:1] device;
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reg is_device;
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begin
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if ((device == "DEVICE2") || (device == "DEVICE 2"))
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is_device = 1;
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else
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is_device = 0;
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is_dev2 = is_device;
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end
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endfunction
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function is_dev;
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input[8*20:1] device;
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reg is_device;
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begin
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// Changing this to a single item makes things work.
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if (is_dev1(device) || is_dev2(device))
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is_device = 1;
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else
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is_device = 0;
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is_dev = is_device;
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end
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endfunction
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assign res = (is_dev(device) == 1) ? 1'b1 : 1'b0;
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initial #1 if (res == 1'b1) $display("PASSED");
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else $display("FAILED");
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endmodule
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