32 lines
517 B
Verilog
32 lines
517 B
Verilog
// Copyright 2008, Martin Whitaker.
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// This file may be freely copied for any purpose.
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module scan_int_array();
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integer f;
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integer i;
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integer n;
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integer v[0:3];
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initial begin
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f = $fopen("work/temp.txt", "w");
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for (i = 0; i < 4; i = i + 1) begin
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$fdisplay(f, "%d", i);
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end
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$fclose(f);
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f = $fopen("work/temp.txt", "r");
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for (i = 0; i < 4; i = i + 1) begin
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n = $fscanf(f, " %d ", v[i]);
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end
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$fclose(f);
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for (i = 0; i < 4; i = i + 1) begin
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$display("%1d", v[i]);
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end
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end
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endmodule
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