30 lines
624 B
Verilog
30 lines
624 B
Verilog
module dummy;
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integer i;
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integer foo_value;
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reg [1:0] foo_bit;
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initial
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begin
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i = 1;
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foo_value = 10;
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foo_bit[i] <= #foo_value 1'b0;
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/*
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NOTE:
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if you replace previous line either with:
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foo_bit[1] <= #foo_value 1'b0;
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or with:
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foo_bit[i] <= #10 1'b0;
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then "invalid opcode" is not shown
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*/
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#20 if (foo_bit[1] !== 1'b0) begin
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$display("FAILED -- foo_bit[1] = %b", foo_bit[1]);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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