24 lines
554 B
Verilog
24 lines
554 B
Verilog
module top;
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wire real result;
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wire [63:0] bits;
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real in;
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assign bits = $realtobits(in);
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// This generates incorrect code:
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// The .net/real temporary is not needed.
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// The .alias/real temporary is not needed.
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// The .sfunc should connect directly to the "results" net.
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// The .part is not needed and is causing a core dump.
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//
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// Once these are fixed it appears there is a concurrency issues
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assign result = $bitstoreal(bits);
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initial begin
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$monitor(result,, bits,, in);
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in = 0.0;
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#1 in = 2.0;
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end
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endmodule
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