28 lines
591 B
Verilog
28 lines
591 B
Verilog
// PR1845683
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/**
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* Author: Evan Lavelle
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* Company: Riverside Machines Ltd.
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* Date: 06/12/2007
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*
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* Cver feature #1; signed arithmetic
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*
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* The correct output should be:
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*
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* res1: '00101010'; res2: '00101010'; res3: '00101010'
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*
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* Cver reports:
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*
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* res1: '10101010'; res2: '10101010'; res3: '10101010'
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*/
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module test;
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reg [7:0] res1, res2;
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reg signed [7:0] res3;
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initial
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begin
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res1 = 8'sb11001100 ^ 7'sb1100110;
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res2 = $signed(8'b11001100) ^ $signed(7'b1100110);
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res3 = $signed(8'b11001100) ^ $signed(7'b1100110);
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$display("res1: '%b'; res2: '%b'; res3: '%b'", res1, res2, res3);
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end
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endmodule
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