94 lines
2.1 KiB
Verilog
94 lines
2.1 KiB
Verilog
`begin_keywords "1364-2005"
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module top;
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reg svar;
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reg sarr [1:0];
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reg sout, stmp;
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wire wsarr [1:0];
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wire wsbslv, wspslv, wsuplv, wsdolv;
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wire wsbstr, wspstr, wsuptr, wsdotr;
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wire wsbs = svar[0];
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wire wsps = svar[0:0];
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wire wsup = svar[0+:1];
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wire wsdo = svar[0-:1];
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wire wsabs = sarr[0][0];
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wire wsaps = sarr[0][0:0];
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wire wsaup = sarr[0][0+:1];
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wire wsado = sarr[0][0-:1];
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assign wsbslv[0] = svar;
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assign wspslv[0:0] = svar;
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assign wsuplv[0+:1] = svar;
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assign wsdolv[0-:1] = svar;
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assign wsarr[0][0] = svar;
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assign wsarr[0][0:0] = svar;
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assign wsarr[0][0+:1] = svar;
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assign wsarr[0][0-:1] = svar;
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tran(wsbstr[0], wsarr[1]);
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tran(wspstr[0:0], wsarr[1]);
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tran(wsuptr[0+:1], wsarr[1]);
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tran(wsdotr[0-:1], wsarr[1]);
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submod1 s1 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]);
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submod2 s2 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]);
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submod3 s3 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]);
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task stask;
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input a;
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reg local;
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begin
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local = a[0];
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local = a[0:0];
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local = a[0+:1];
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local = a[0-:1];
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end
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endtask
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initial begin
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stmp = svar[0];
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stmp = svar[0:0];
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stmp = svar[0+:1];
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stmp = svar[0-:1];
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stmp = sarr[0][0];
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stmp = sarr[0][0:0];
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stmp = sarr[0][0+:1];
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stmp = sarr[0][0-:1];
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sout[0] = 1'b0;
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sout[0:0] = 1'b0;
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sout[0+:1] = 1'b0;
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sout[0-:1] = 1'b0;
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sarr[0][0] = 1'b0;
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sarr[0][0:0] = 1'b0;
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sarr[0][0+:1] = 1'b0;
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sarr[0][0-:1] = 1'b0;
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end
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endmodule
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module submod1(arg1, arg2, arg3, arg4);
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input arg1, arg2, arg3, arg4;
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wire arg1, arg2, arg3, arg4;
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initial $display("In submod1 with %b, %b, %b, %b", arg1, arg2, arg3, arg4);
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endmodule
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module submod2(arg1, arg2, arg3, arg4);
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output arg1, arg2, arg3, arg4;
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wire arg1, arg2, arg3, arg4;
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initial $display("In submod2 with %b, %b, %b, %b", arg1, arg2, arg3, arg4);
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endmodule
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module submod3(arg1, arg2, arg3, arg4);
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inout arg1, arg2, arg3, arg4;
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wire arg1, arg2, arg3, arg4;
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initial $display("In submod3 with %b, %b, %b, %b", arg1, arg2, arg3, arg4);
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endmodule
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`end_keywords
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