41 lines
971 B
Verilog
41 lines
971 B
Verilog
module test;
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reg fail = 0;
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reg [3:0] in = 4'b0;
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wire [3:0] bus = in;
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initial begin
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#1; // Need some delay for the calculations to run.
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if (bus !== 4'b0) begin
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$display("FAILED: initial value, got %b, expected 0000.", bus);
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fail = 1;
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end
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#1 force bus[0] = 1'b1;
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#1 in[0] = 1'bz;
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if (bus !== 4'b0001) begin
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$display("FAILED: force of bus[0], got %b, expected 0001.", bus);
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fail = 1;
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end
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#1 force bus[3:2] = 2'b11;
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if (bus !== 4'b1101) begin
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$display("FAILED: force of bus[3:2], got %b, expected 1101.", bus);
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fail = 1;
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end
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#1 release bus[0];
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if (bus !== 4'b110z) begin
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$display("FAILED: release of bus[0], got %b, expected 110z.", bus);
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fail = 1;
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end
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#1 release bus[3:2];
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if (bus !== 4'b000z) begin
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$display("FAILED: release of bus[3:2], got %b, expected 000z.", bus);
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fail = 1;
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end
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if (!fail) $display("PASSED");
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end
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endmodule
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