32 lines
652 B
Verilog
32 lines
652 B
Verilog
module test;
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// parameter j=0;
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reg [5:0] j;
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reg [5:0] in [7:0];
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wire [5:0] out [7:0];
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assign out[0][1:0] = 2'b10;
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assign out[0][3:2] = 2'b01;
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assign out[1] = in[j]; // This uses the current j!
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assign out[2] = in[2];
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assign out[3] = in[3];
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initial begin
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j = 1;
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in[j] = 2'b10;
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in[2][3:2] = 2'b01;
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in[j+2][3:2] = 2'b10;
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#1;
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$display("out[0]: %b", out[0]);
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$display("out[1]: %b", out[1]);
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$display("out[2]: %b", out[2]);
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$display("out[3]: %b", out[3]);
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for (j=0; j<4; j=j+1) begin
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#0; // wait for change to propagate
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$display("out[1]-%0d: %b", j, out[1]);
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end
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end
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endmodule
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