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luke
/
iverilog
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a7c5eceeea
iverilog
/
ivtest
/
ivltests
/
pr1792152.v
5 lines
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Verilog
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module
top
;
parameter
value
=
(
1
:
2
:
3
)
;
initial
$display
(
value
)
;
endmodule
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