40 lines
751 B
Verilog
40 lines
751 B
Verilog
// pr1784984
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module signed_test;
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reg [31:0] a;
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initial begin
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a = (32'h80000000);
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a = a / 2;
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$display ("Current Value of a = %h", a);
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if (a !== 32'h40000000) begin
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$display("FAILED");
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$finish;
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end
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a = a * 2;
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$display("Current value of a = %h", a);
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if (a !== 32'h80000000) begin
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$display("FAILED");
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$finish;
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end
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a = (32'h80000000)/2;
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$display ("Current Value of a = %h", a);
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if (a !== 32'h40000000) begin
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$display("FAILED");
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$finish;
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end
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a = (32'h40000000)*2;
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$display ("Current Value of a = %h", a);
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if (a !== 32'h80000000) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // signed_test
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