34 lines
639 B
Verilog
34 lines
639 B
Verilog
// pr1776485.v
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module vvp_fun_and;
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wire [7:0] ADC_gain;
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reg [7:0] force_low;
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wire [7:0] adc_gain_out = ADC_gain & ~force_low;
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UXO source(ADC_gain[5:0]);
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initial begin
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force_low = 0;
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#1 $display("ADC_gain = %b, acd_gain_out = %b", ADC_gain, adc_gain_out);
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if (ADC_gain !== 8'bzz_101010) begin
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$display("FAILED -- ADC_gain=%b", ADC_gain);
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$finish;
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end
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if (adc_gain_out !== 8'bxx_101010) begin
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$display("FAILED -- adc_gain_out=%b", adc_gain_out);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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module UXO(output [5:0] gain);
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assign gain = 6'b101010;
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endmodule
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