23 lines
385 B
Verilog
23 lines
385 B
Verilog
// pr1765789
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module main;
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reg [32:0] addr = {1'b1, 32'h0040_0000 + 32'h8};
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initial begin
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#1 ;
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if (addr !== 33'h1_0040_0008) begin
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$display("FAILED -- addr = %h", addr);
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$finish;
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end
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if ($bits({32'h0040_0000 + 32'h8}) !== 32) begin
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$display("FAILED -- bits count wrong");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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