36 lines
616 B
Verilog
36 lines
616 B
Verilog
module test;
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parameter some = 4;
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wire [some-1:0] flag1;
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genvar i;
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generate
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for (i = 0; i < some; i = i + 1)
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begin : what
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wire [some-1:0] slice;
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end
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endgenerate
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generate
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for (i = 0; i < some; i = i + 1)
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begin : ab
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assign what[i].slice[i] = 1'b1;
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assign flag1[i] = &what[i].slice;
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end
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endgenerate
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integer idx;
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initial #1 begin
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for (idx = 0 ; idx < some ; idx = idx+1) begin
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if (flag1[idx] !== 1'bx) begin
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$display("FAILED -- flag1=%b", flag1);
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$finish;
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end
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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