24 lines
389 B
Verilog
24 lines
389 B
Verilog
module test();
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reg [1:0] array[1:0];
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reg sign;
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reg clk = 1'b0;
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always @(posedge clk)
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sign = array[1][1];
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initial begin
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array[0] = 1;
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array[1] = 2;
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#1 clk = 1;
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#1 if (sign !== 1'b1) begin
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$display("FAILED -- array[1][1] = %b, sign=%b", array[1][1], sign);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // test
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