35 lines
659 B
Verilog
35 lines
659 B
Verilog
module main;
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wire [3:0] src [15:0];
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wire [3:0] dst [15:0];
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genvar i;
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for (i = 0 ; i < 16; i = i+1) begin:bb
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buffer u (.out(dst[i]), .in(src[i]));
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end
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for (i = 0 ; i < 16 ; i = i+1) begin:drv
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assign src[i] = i;
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end
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integer idx;
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initial begin
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#1 ;
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for (idx = 0 ; idx < 16 ; idx = idx+1) begin
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if (dst[idx] !== idx) begin
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$display("FAILED -- src[%0d]==%b, dst[%0d]==%b",
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idx, src[idx], idx, dst[idx]);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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module buffer (input wire [3:0] in, output wire [3:0] out);
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assign out = in;
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endmodule // buffer
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