24 lines
429 B
Verilog
24 lines
429 B
Verilog
// pr1701921
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module top;
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reg foo, bar;
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wire blend;
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assign blend = foo;
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assign blend = bar;
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initial begin
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bar = 1;
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// Bar explicitly has a 1 value, foo gets its initial x value.
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// Together, they should drive to an x value.
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#1 if (blend !== 1'bx) begin
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$display("FAILED -- blend=%b (foo=%b, bar=%b)", blend, foo, bar);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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