iverilog/ivtest/ivltests/pr1701890.v

9 lines
166 B
Verilog

module top;
real rval1=1.0, rval2=2.0;
realtime rtval=1.0;
initial begin
$display("rval1=", rval1,,"rval2=", rval2,,"rtval=",rtval);
end
endmodule