37 lines
710 B
Verilog
37 lines
710 B
Verilog
`timescale 1us/1ns
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module top;
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initial begin
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// This should print the following:
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// Time scale of (top) is 1us / 1ns
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// Time scale of (top) is 1us / 1ns
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// Time scale of (top.dut) is 10ns / 10ps
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// Time scale of (top.dut.dut) is 1ns / 10ps
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// Time scale of (othertop) is 1ms / 1us
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// But currently the precisions will all be 10ps the finest precision.
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$printtimescale;
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$printtimescale();
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$printtimescale(dut);
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$printtimescale(dut.dut);
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$printtimescale(othertop);
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end
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lower dut();
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endmodule
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`timescale 10ns/10ps
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module lower;
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evenlower dut();
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endmodule
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`timescale 1ns/10ps
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module evenlower;
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endmodule
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`timescale 1ms/1us
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module othertop;
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endmodule
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