40 lines
779 B
Verilog
40 lines
779 B
Verilog
`timescale 1ns/10ps
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module top;
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reg topvar;
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initial begin
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topvar = 0;
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lwr.lowervar = 1;
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lwr.elwr.evenlowervar = 0;
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othertop.othertopvar = 1;
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#10 $display("%m var is (%b)", topvar);
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end
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lower lwr();
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endmodule
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module lower;
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reg lowervar;
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initial begin
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#11 $display("%m var is (%b)", lowervar);
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end
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evenlower elwr();
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endmodule
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module evenlower;
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reg evenlowervar;
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initial begin
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#12 $display("%m var is (%b)", evenlowervar);
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$display("Up reference to me (%b)", elwr.evenlowervar);
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$display("Up reference to parent (%b)", lwr.lowervar);
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$display("Up reference is (%b)", lower.lowervar);
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end
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endmodule
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module othertop;
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reg othertopvar;
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initial begin
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#20 $display("%m var is (%b)", othertopvar);
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end
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endmodule
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