26 lines
567 B
Verilog
26 lines
567 B
Verilog
////
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//// The following was written to illustrate a bug in iverilog.
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//// In particular, this little lovely produces a 202 MB vvp file.
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////
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module ExplodedArrays1;
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reg [7:0] data [0:25600-1];
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integer idx;
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initial begin
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for (idx = 0 ; idx < 25600 ; idx = idx+1)
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data[idx] = idx[7:0];
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for (idx = 0 ; idx < 256 ; idx = idx+ 1) begin
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if (data[idx] !== idx) begin
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$display("FAILED -- data[%d] = %d (%h)", idx, data[idx], data[idx]);
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$finish;
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end
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end
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$display("PASSED");
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end // initial begin
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endmodule
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