38 lines
760 B
Verilog
38 lines
760 B
Verilog
module test;
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reg [3:0] foo;
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reg [3:0] shift;
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wire [3:0] rs = foo >> shift;
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wire [3:0] ls = foo << shift;
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wire tr = 4'b0100 > (foo >> shift);
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initial begin
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foo = 4'b1001;
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shift = 0;
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#1 if (rs !== 4'b1001 || ls !== 4'b1001) begin
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$display("FAILED -- shift=%d, rs=%b, ls=%b", shift, rs, ls);
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$finish;
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end
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shift = 1;
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#1 if (rs !== 4'b0100 || ls !== 4'b0010 || tr !== 0) begin
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$display("FAILED -- shift=%d, rs=%b, ls=%b", shift, rs, ls);
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$finish;
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end
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shift = 2;
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#1 if (rs !== 4'b0010 || ls !== 4'b0100 || tr !== 1) begin
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$display("FAILED -- shift=%d, rs=%b, ls=%b", shift, rs, ls);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule
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