44 lines
733 B
Verilog
44 lines
733 B
Verilog
module test;
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integer dindex[2:0];
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integer cindex[2:0];
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initial
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main;
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task main;
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integer index;
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begin
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dindex[0] = 3;
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dindex[1] = 4;
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dindex[2] = 5;
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cindex[0] = 1;
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cindex[1] = 2;
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cindex[2] = 3;
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index = get_index(3);
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$write("index is %0d\n", index);
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if (index !== 32)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endtask
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function integer get_index;
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input rank;
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integer rank;
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integer i, sum, multiplier;
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begin
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multiplier = 1;
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sum = 0;
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for(i = rank-1; i >= 0; i = i-1) begin
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sum = sum + (cindex[i] * multiplier);
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multiplier = dindex[i] * multiplier;
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end
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get_index = sum-1;
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end
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endfunction
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endmodule // test
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