66 lines
865 B
Verilog
66 lines
865 B
Verilog
module ivitest;
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reg clock_1x, clock_2x;
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reg [31:1] w [0:1];
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wire [31:1] w0 = w[0];
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wire [31:1] w1 = w[1];
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initial begin
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#0; //avoid time-0 race
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clock_1x = 0;
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clock_2x = 0;
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$monitor($time,,"w0=%h, w1=%h", w0, w1);
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#1;
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forever begin
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clock_1x = !clock_1x;
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clock_2x = !clock_2x;
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#5;
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clock_2x = !clock_2x;
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#5;
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end
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end
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reg phase;
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always @(clock_1x) begin
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phase = #1 clock_1x;
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end
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reg [31:1] u;
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always @(posedge clock_2x) begin
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u <= 'haaaaaaaa;
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end
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reg [31:1] v;
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always @(posedge clock_2x) begin
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v <= 'h99999999;
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if (phase) begin
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w[0] <= v;
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w[1] <= u;
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end
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end
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reg [31:1] x0, x1;
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always @(posedge clock_1x) begin
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x0 <= w[0];
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x1 <= w[1];
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end
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initial begin
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// $dumpfile( "test.vcd" );
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// $dumpvars;
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#100;
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$finish(0);
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end
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endmodule
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