34 lines
745 B
Verilog
34 lines
745 B
Verilog
/* PR1645518 */
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module testBench;
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wire w1, w2, w3, w4, w5;
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binaryToESeg d (w1, w2, w3, w4, w5);
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test_bToESeg t (w1, w2, w3, w4, w5);
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endmodule
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module binaryToESeg
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(input A, B, C, D,
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output eSeg);
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nand #1
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g1 (p1, C, ~D),
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g2 (p2, A, B),
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g3 (p3, ~B, ~D),
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g4 (p4, A, C),
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g5 (eSeg, p1, p2, p3, p4);
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endmodule // binaryToESeg
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module test_bToESeg
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(output reg A, B, C, D, input eSeg);
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initial // two slashes introduce a single line comment
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begin
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$monitor ($time,,
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"A = %b B = %b C = %b D = %b, eSeg = %b",
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A, B, C, D, eSeg);
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//waveform for simulating the nand lip lop
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#10 A = 0; B = 0; C = 0; D = 0;
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#10 D = 1;
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#10 C = 1; D = 0;
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#10 $finish(0);
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end
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endmodule
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